A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC

• Main Authors: Nayak, Ashish, Chen, HsinChen, Mair, Hugh, Lagerquist, Rolf, Chen, Tao, Rajagopalan, Anand, Gammie, Gordon, Madhavaram, Ramu, Jagota, Madhur, Chung, CJ, Wiedemeier, Jenny, Meera, Bala, Yeh, Chao-Yang, Lin, Maverick, Lin, Curtis, Lin, Vincent, Lin, Jiun, Chen, YS, Chen, Barry, Wu, Cheng-Yuh, ChangChien, Ryan, Tzeng, Ray, Yang, Kelvin, Thippana, Achuta, Wang, Ericbill, Hwang, SA
• Format: Conference Proceeding
• Language: English
• Subjects: 5G mobile communication; Central Processing Unit; Graphics processing units; Image resolution; Modems; Streaming media; Three-dimensional displays
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC42614.2022.9731604

This paper presents a tri-gear ARMv9 CPU subsystem incorporated in a 5G flagship mobile SoC. Implemented in a 5nm technology node, a 3.4GHz High-Performance (HP) core is introduced along with circuit and implementation techniques to achieve CPU PPA targets. A die photograph is shown in Fig. 2.5.7. The SoC integrates a 5G modem supporting NR sub-6GHz with downlink and uplink speed up to 7.01Gb/s and 2.5Gb/s, respectively, an ARMv9 CPU subsystem, an ARM Mali G710 GPU for 3D graphics, an in-house Vision Processing Unit (VPU), and a Deep-Learning Accelerator (DLA) for high-performance and power-efficient AI processing. The integrated display engine can provide portrait panel resolution up to QHD+ 21:9 (1600\times 3360) and frame rates up to 144Hz. Multimedia and imaging subsystems decode 8K video at 30fps, while encoding 4K video at 60fps; camera resolutions up to 320MPixels are supported. LPDDR5-6400/LPDDR5X-7500 memory interfaces facilitate up to 24GB of external SDRAM over four 16b channels for a peak transfer rate of 0.46Tb/s.