Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor

Shrinking transistor sizes allow increased logic complexity in modern processors, but smaller dimensions increase power density and require reduced maximum voltage (\text{VDD}_{\text{MAX}}) for reliability; this can severely limit the performance achievable in new technologies. Three techniques incr...

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Bibliographic Details
Main Authors: Vanderpool, Brian T., Restle, Phillip J., Fluhr, Eric J., Still, Gregory S., Campisano, Frank, Carmichael, Ian, Marz, Eric, Batra, Rahul, Willaman, Richard
Format: Conference Proceeding
Language:English
Subjects:
Complexity theory
Conferences
Density measurement
Power system measurements
Program processors
Transistors
Voltage control
Online Access:Request full text
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Summary:Shrinking transistor sizes allow increased logic complexity in modern processors, but smaller dimensions increase power density and require reduced maximum voltage (\text{VDD}_{\text{MAX}}) for reliability; this can severely limit the performance achievable in new technologies. Three techniques increase performance of the POWER10™ processor, built on Samsung 7nm technology, within these constraints: (a) a Workload-Optimized Frequency (WOF) algorithm to maximize frequency within the power envelope, (b) Core Logic Voltage (VDD) droop mitigation using a Digital Droop Sensor (DDS) with core throttling, and (c) Undervolt - a voltage control loop using the DDS to offset loadline uplift and voltage gradients and noise effects to maintain VDD below \text{VDD}_{\text{MAX}} .
ISSN:2376-8606
DOI:10.1109/ISSCC42614.2022.9731746