A BER-Suppressed PUF With an Amplification of Process Mismatch Effect in an Oscillator Collapse Topology

• Published in: IEEE journal of solid-state circuits 2022-07, Vol.57 (7), p.2208-2219
• Main Authors: Park, Jaehan, Kim, ByungJun, Sim, Jae-Yoon
• Format: Article
• Language: English
• Subjects: Amplification; Amplifiers; Analytical models; Bit error rate; Challenge–response pair (CRP); Computer architecture; Delays; hardware security; Immunity; Inverters; key generation; Oscillators; physically unclonable function (PUF); process variation; Signal processing; Topology
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2022.3157811

The physically unclonable function (PUF) has been implemented with circuits that perform amplification of randomly given small process mismatch by using an explicit amplifier or by making a signal path repeatedly experience the same delay skew in an oscillator. Though the amplifier approach provides a fast response, it is vulnerable to noise at the first stage of amplification. On the other hand, the oscillator-based scheme requires a longer time to develop a digital output while achieving good noise immunity. This article proposes a PUF circuit exploiting a hybrid architecture, which combines a process skew amplification scheme in an oscillator collapse topology. The proposed scheme compensates for the drawbacks of the two approaches while achieving merits of them, i.e., high sensitivity to process variation and good immunity to noise. The supply rails of an even-stage ring oscillator (RO) are alternately fed from a diode-based threshold-sampling block. An IC with an array of 128 PUF cells is fabricated in 40-nm CMOS, showing a native bit error rate (BER) of 0.027%. Processing of 7-b temporal majority voting (TMV7) with a 3.64% masking demonstrates an error-free operation in a nominal condition. It shows a BER of 0.0019% in the worst condition under a voltage range of 0.7-1.4 V and a temperature range of −40 °C to 125 °C.