ReMCA: A Reconfigurable Multi-Core Architecture for Full RNS Variant of BFV Homomorphic Evaluation

Fully homomorphic encryption (FHE) allows arbitrary computation on encrypted data and thus has potential in privacy-preserving computing. However, efficiency is still the bottleneck. In this paper we present an area-efficient and highly unified reconfigurable multi-core architecture (named ReMCA) fo...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2022-07, Vol.69 (7), p.2857-2870
Main Authors: Su, Yang, Yang, Bai-Long, Yang, Chen, Zhao, Song-Yin
Format: Article
Language:English
Subjects:
Arithmetic
BFV scheme
Computation
Computational modeling
Computer architecture
Computer memory
Cryptography
Encryption
Field programmable gate arrays
Hardware
Homomorphic encryption
multi-core architecture
Multiplication
NTT/INTT
Number systems
reconfigurable PE
Reconfiguration
Residue number systems
RNS
Software
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Summary:Fully homomorphic encryption (FHE) allows arbitrary computation on encrypted data and thus has potential in privacy-preserving computing. However, efficiency is still the bottleneck. In this paper we present an area-efficient and highly unified reconfigurable multi-core architecture (named ReMCA) for full Residue Number System (RNS) variant of Fan-Vercauteren variant of Brakerski's scheme (RNS-BFV), which employs a variable number of reconfigurable processing elements (PEs) and RNS channels. The PE unit can be flexibly configured as NTT, INTT or modular multiplier, thereby avoiding the need of other extra computational units. To reduce the computational complexity, ReMCA merges the pre/post-processing into NTT/INTT and unifies the read/write structure of NTT and INTT. Also, a conflict-free memory access pattern that doesn't need separate bit-reversal operation is proposed to optimize the memory access. Furthermore, targeting different computational requirements, a unified hardware architecture mapping model and data memory organization model are introduced, and all the computing units that RNS-BFV involved are optimized and mapped on ReMCA. ReMCA is evaluated on a Xilinx Virtex-7 FPGA platform. Running at 250MHz, it can perform 2260 homomorphic multiplication per second. When normalized to the same parameter set, the throughput and Area-Time-Products (ATPs) of ReMCA achieve 1.45\times \sim 5.51\times and 1.58\times \sim 5.12\times improvements.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2022.3163970