Fully Parallel Stochastic Computing Hardware Implementation of Convolutional Neural Networks for Edge Computing Applications

• Published in: IEEE transaction on neural networks and learning systems 2023-12, Vol.34 (12), p.10408-10418
• Main Authors: Frasser, Christiam F., Linares-Serrano, Pablo, de Rios, Ivan Diez de los, Moran, Alejandro, Skibinsky-Gitlin, Erik S., Font-Rossello, Joan, Canals, Vincent, Roca, Miquel, Serrano-Gotarredona, Teresa, Rossello, Josep L.
• Format: Article
• Language: English
• Subjects: Artificial intelligence; Artificial neural networks; Computer architecture; Convolutional neural networks; Convolutional neural networks (CNNs); Correlation; Deep learning; Edge computing; edge computing (EC); Europe; Field programmable gate arrays; Hardware; Integrated circuits; Internet of Things; Logic gates; Machine learning; Neural networks; stochastic computing (SC); Stochastic systems; Stochasticity
• ISSN: 2162-237X; 2162-2388
• DOI: 10.1109/TNNLS.2022.3166799

Edge artificial intelligence (AI) is receiving a tremendous amount of interest from the machine learning community due to the ever-increasing popularization of the Internet of Things (IoT). Unfortunately, the incorporation of AI characteristics to edge computing devices presents the drawbacks of being power and area hungry for typical deep learning techniques such as convolutional neural networks (CNNs). In this work, we propose a power-and-area efficient architecture based on the exploitation of the correlation phenomenon in stochastic computing (SC) systems. The proposed architecture solves the challenges that a CNN implementation with SC (SC-CNN) may present, such as the high resources used in binary-to-stochastic conversion, the inaccuracy produced by undesired correlation between signals, and the complexity of the stochastic maximum function implementation. To prove that our architecture meets the requirements of edge intelligence realization, we embed a fully parallel CNN in a single field-programmable gate array (FPGA) chip. The results obtained showed a better performance than traditional binary logic and other SC implementations. In addition, we performed a full VLSI synthesis of the proposed design, showing that it presents better overall characteristics than other recently published VLSI architectures.