A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS

• Main Authors: Runge, Marcel, Edler, Julius, Schmock, Dario, Kaiser, Tobias, Gerfers, Friedel
• Format: Conference Proceeding
• Language: English
• Subjects: Computer architecture; Logic gates; Microprocessors; Modulation; Receivers; Silicon-on-insulator; Wireless communication
• ISSN: 2152-3630
• DOI: 10.1109/CICC53496.2022.9772799

Wide-band, power-efficient continuous-time (CT) \Delta\Sigma modulators have become the core building block for modern wireless receiver architectures. In particular, the multi-bit \Delta\Sigma modulator topology is very popular compared to the single-bit variant, as this not only enables a reduced oversampling ratio (OSR) for a given bandwidth and SNDR but also leads to significant power savings. However, as multi-bit DACs are inherently non-linear, these errors fundamentally limit the linearity of the entire modulator. State of the art analog correction concepts [1] compensate multi-bit DAC errors by placing an auxiliary DAC (AUXDAC) in parallel to the main feedback DAC. The AUXDAC operates at full modulator clock speed, giving rise to four major drawbacks highlighted in Fig. 1. This work proposes a body-bias DAC calibration scheme that overcomes all these drawbacks by utilizing the transistor back gate as a control node to correct static DAC unit cell mismatch to 15bit accuracy.