A Memory Efficient FPGA Implementation of Offset-Free Explicit Model Predictive Controller

In the explicit model predictive control (EMPC), memory increases exponentially with the number of states, inputs, constraints, and prediction horizons; this often limits its applicability to large systems. In this article, we present a novel memory reduction technique for the lightweight EMPC using...

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Bibliographic Details
Published in:IEEE transactions on control systems technology 2022-11, Vol.30 (6), p.2646-2657
Main Authors: Jugade, Chaitanya, Ingole, Deepak, Sonawane, Dayaram N., Kvasnica, Michal, Gustafson, John
Format: Article
Language:English
Subjects:
Anesthesia
Disturbance modeling
Embedded systems
Field programmable gate arrays
Floating point arithmetic
floating-point
Hardware-in-the-loop simulation
model predictive control (MPC)
offset-free control
Optimization
posit number format
Power management
Predictive control
Reduction
Resource utilization
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Summary:In the explicit model predictive control (EMPC), memory increases exponentially with the number of states, inputs, constraints, and prediction horizons; this often limits its applicability to large systems. In this article, we present a novel memory reduction technique for the lightweight EMPC using a novel posit number format implemented on a field-programmable gate array (FPGA), aiming to reduce the memory footprints and power utilization of the EMPC. We developed a fully automatic framework for the design of fast embedded EMPC on FPGAs using posit arithmetic and logical unit (ALU). The proposed technique is based on encoding all data (i.e., the critical regions and the feedback laws) as posit numbers, which can be viewed as a more memory-efficient alternative to the IEEE 754 floating-point standard. The performance and efficiency of the developed posit-based offset-free EMPC are demonstrated on the anesthesia control problem. We show the results of hardware-in-the-loop co-simulation with the detailed analysis of the resource utilization, power utilization, clock achieved, and the memory footprints comparison between IEEE 754 floating-point and posit formats. By doing so, we illustrate that the total memory footprints can be reduced by 50%-75% with achieving low power utilization as compared to floating-point numbers without sacrificing the control performances. The proposed technique can be applied on top of other existing complexity reduction techniques used in EMPC as well as for the online optimization methods.
ISSN:1063-6536
1558-0865
DOI:10.1109/TCST.2022.3168493