A Low-Power Column-Parallel ΣΔ ADC With Shared OTAs and Single-Bit-BWI Decimation Filter for CMOS Image Sensor

• Published in: IEEE transactions on electron devices 2022-06, Vol.69 (6), p.2979-2985
• Main Authors: Wang, Zhongjie, Ma, Qiyun, Yang, Tongbei, Lin, Zhi, Bermak, Amine, Tang, Fang
• Format: Article
• Language: English
• Subjects: Analog to digital converters; Analog-digital conversion; Capacitors; Clocks; CMOS; CMOS image sensor (CIS); column-parallel readout circuit; Columnar structure; Crosstalk; digital decimation filter; Digital imaging; Figure of merit; Image filters; Image resolution; low power; Modulation; Nonlinearity; Operational amplifiers; Pixels; Power consumption; Power demand; Power management; Registers; Sensors; shared operational transconductance amplifier (OTA); Time division multiplexing; Topology; Transconductance; ΣΔ analog-to-digital converter (ADC)
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2022.3171742

This article presents a low-power column-parallel \Sigma \Delta analog-to-digital converter (ADC) with shared operational transconductance amplifiers (OTAs) for CMOS image sensors (CISs). Through the proposed time division multiplexing of OTAs, the power consumption of the modulator achieves a reduction of about 40%. The proposed structure alleviates the layout requirement of OTAs, enabling implementation of a high-resolution low-power image sensor in advanced CMOS technology nodes. As the coupled noise introduced by the proposed column-shared scheme is suppressed to a lower level than the inherent crosstalk of adjacent pixels, the proposed structure only contributes a negligible inter-column coupled noise from the ADCs. Moreover, a compact digital decimation filter with a single-bit-bit-wise-inversion (BWI) topology is also proposed, which can reduce chip area significantly. The prototype sensor is fabricated in a 40-nm standard CMOS technology with 256 \times256 pixel array and 256 proposed column-parallel \Sigma \Delta ADCs. Each \Sigma \Delta ADC occupies a core area of 4.5 \mu \text{m}\,\,\times 310 \mu \text{m} , while consuming a power of 58.8 \mu \text{W} . The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.49/−0.65 LSB and +5.1/−4.8 LSB, respectively. Measurement results show a dynamic range of 79.9 dB and an effective-number-of-bit (ENOB) of 11.4 bit. This work achieves a figure of merit (FOM) of 97.2 fJ/step.