FPGA-assisted Massive Packet Queueing and Traffic Shaping at the Network Edge

Large-scale packet queueing and scheduling is the basis for today's Quality of Service (QoS) in computer access networks, especially to achieve guaranteed high throughput and low latency. While highly performant fixed-function ASICs offer sufficient functionality for most data center use-cases,...

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Bibliographic Details
Main Authors: Kundel, Ralf, Nobach, Leonhard, Kolbe, Hans-Joerg, Meuser, Tobias, Steinmetz, Ralf
Format: Conference Proceeding
Language:English
Subjects:
AQM
Computer architecture
Data centers
FPGA
Internet
Network Function Offloading
Processor scheduling
QoS
Quality of service
Queueing
Scheduling
Throughput
Traffic Shaping
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Description
Summary:Large-scale packet queueing and scheduling is the basis for today's Quality of Service (QoS) in computer access networks, especially to achieve guaranteed high throughput and low latency. While highly performant fixed-function ASICs offer sufficient functionality for most data center use-cases, as of today, they cannot support all functionality required for access networks, e.g., QoS-aware packet queueing.In this poster, we present an FPGA-based architecture for network packet queueing optimized for residential and mobile Internet access networks.
ISSN:2576-2621
DOI:10.1109/FCCM53951.2022.9786068