NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links

MATHS (Mechanism to Access Test-Data over High-Speed Link) provides a high-throughput PCIe based system to structurally test system-on-chips (SOCs) at wafer and system-level. The system removes the need for expensive test equipment by eliminating the input/output pin (IO) requirements and memory per...

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Bibliographic Details
Main Authors: Yilmaz, Mahmut, Jagannadha, Pavan Kumar Datla, Narayanun, Kaushik, Sarangi, Shantanu, Da Silva, Francisco, Sarmiento, Joe, Tonoyan, Smbat, Chintaluri, Ashwin, Khare, Animesh, Sonawane, Milind, Kumar, Ashish, Kalva, Anitha, Hsu, Alex, Pandey, Jayesh
Format: Conference Proceeding
Language:English
Subjects:
ATE
Costs
high-speed interface
in-system test
Memory management
PCIE
Pins
SLT
System-on-chip
Test equipment
test-access mechanism
Very large scale integration
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Summary:MATHS (Mechanism to Access Test-Data over High-Speed Link) provides a high-throughput PCIe based system to structurally test system-on-chips (SOCs) at wafer and system-level. The system removes the need for expensive test equipment by eliminating the input/output pin (IO) requirements and memory per IO needs. It simplifies the ATE architecture and design to enable smaller form factors and reduce capital costs of ownership. MATHS enables eliminating the assembly test-insertion by directly testing the SOCs on system level platforms, further reducing the costs. Since the mechanism is based on PCIe standards, it is highly portable across all platforms including ATE, system-level test, board, and in-field testing.
ISSN:2375-1053
DOI:10.1109/VTS52500.2021.9794146