Heterogeneous Logic Implementation for Adders in VTR

• Main Authors: Kaur, Harpreet, Krylov, Georgiy, Damghani, Seyed Alireza, Kent, Kenneth B.
• Format: Conference Proceeding
• Language: English
• Subjects: CAD; Conferences; Delays; Design automation; FPGA; hard adder; Hardware design languages; ODIN II; Optimization; Performance gain; simulation; soft adder; synthesis; VTR
• ISSN: 2150-5519
• DOI: 10.1109/RSP53691.2021.9806205

Verilog-to-Routing (VTR) is a Field-Programmable Gate Array (FPGA) Computer-Aided Design (CAD) tool. It is composed of three tools, namely ODIN II, ABC and VPR with each performing distinctive optimizations at different stages of the design flow. The elaboration and hard block synthesis stage of VTR is the core responsibility of the sub-project ODIN II. This work enables ODIN II to use fewer hard adders in the circuit by allowing soft logic implementation alongside hard logic for circuits featuring addition operations. This is particularly useful in scenarios where a sufficient number of hard blocks are not available. The results of applying our modifications to ODIN II as well as the entire VTR flow have been analysed. The results reveal the potential of current adder optimizations to achieve up to 17% performance gains in terms of critical path delays. Another effect of the optimization is the implications on the resulting device size. Some future prospects in this respect are also outlined in this paper.