A High-Resolution SAR ADC Design with Linearity Enhancement Achieving Signal-to-Noise-and- Distortion-Ratio of 97.4dB

Spaceborne industry and medical imaging equipment have been developed rapidly these years, resulting in the demand for system performance, integration level and energy efficiency in their signal chains. SAR ADCs that reside in the region where it runs faster than 1MS/s with 16-bit to 18-bit resoluti...

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Bibliographic Details
Main Authors: Chen, Zulin, Wang, Zongmin, Zhang, Tieliang, Yang, Song, Yang, Long
Format: Conference Proceeding
Language:English
Subjects:
bit weights error
Calibration
foreground calibration
Linearity
mismatch
offset
Registers
Semiconductor device modeling
Simulation
successive approximation
System performance
Voltage
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Summary:Spaceborne industry and medical imaging equipment have been developed rapidly these years, resulting in the demand for system performance, integration level and energy efficiency in their signal chains. SAR ADCs that reside in the region where it runs faster than 1MS/s with 16-bit to 18-bit resolution have good prospects in these fields. A high-resolution SAR ADC with Signal-to-Noise-and-Distortion-Ratio (SNDR) enhanced by digital calibration is proposed based on the 0.25 \mu \mathrm{m} Mixed-Signal CMOS process, using a 5V external reference while the digital works in 2.5V. Design issues across voltage domains are discussed. SPECTRE and MATLAB tools are used for modeling and simulation. Results show that the SNDR is 70.8dB before calibration, which gives an ENOB value of 11.47-bit. While after calibration, the SNDR is 97.4dB, reaches an ENOB value of 15.88-bit.
ISSN:2768-6515
DOI:10.1109/ICET55676.2022.9824365