High Performance and Low Power Spintronic Binarized Neural Network Hardware Accelerator

Neural networks have shown a high ability to model and solve complex problems. Hardware implementation of the neural network can also increase the efficiency of this system and, in particular neural network hardware accelerators. This paper proposes a high-performance and low-power spintronic binari...

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Bibliographic Details
Main Authors: Nasab, Milad Tanavardi, Amirany, Arefe, Moaiyeri, Mohammad Hossein, Jafari, Kian
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Binarized neural network hardware accelerator
CNTFET
Hardware
Low power design
Memory management
MTJ
Neural network hardware
Nonvolatile memory
Power demand
Simulation
System performance
XNOR-Net
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Summary:Neural networks have shown a high ability to model and solve complex problems. Hardware implementation of the neural network can also increase the efficiency of this system and, in particular neural network hardware accelerators. This paper proposes a high-performance and low-power spintronic binarized neural network hardware accelerator using the nonvolatile feature of the magnetic tunnel junction (MTJ) and low leakage current of carbon nanotube field-effect transistors (CNTFET). It is also noteworthy that the proposed design in this paper can implement the hard-limit activation function. Simulation results indicate the neural network implemented using the proposed design in this paper consumes 11% to 98% lower power, occupies 64% to 69% lower area, and offers 29% to 99% lower power delay area product (PDAP) than the state-of-the-art counterparts.
ISSN:2642-9527
DOI:10.1109/ICEE55646.2022.9827189