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High Performance and Low Power Spintronic Binarized Neural Network Hardware Accelerator
Neural networks have shown a high ability to model and solve complex problems. Hardware implementation of the neural network can also increase the efficiency of this system and, in particular neural network hardware accelerators. This paper proposes a high-performance and low-power spintronic binari...
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| creator | Nasab, Milad Tanavardi Amirany, Arefe Moaiyeri, Mohammad Hossein Jafari, Kian |
| description | Neural networks have shown a high ability to model and solve complex problems. Hardware implementation of the neural network can also increase the efficiency of this system and, in particular neural network hardware accelerators. This paper proposes a high-performance and low-power spintronic binarized neural network hardware accelerator using the nonvolatile feature of the magnetic tunnel junction (MTJ) and low leakage current of carbon nanotube field-effect transistors (CNTFET). It is also noteworthy that the proposed design in this paper can implement the hard-limit activation function. Simulation results indicate the neural network implemented using the proposed design in this paper consumes 11% to 98% lower power, occupies 64% to 69% lower area, and offers 29% to 99% lower power delay area product (PDAP) than the state-of-the-art counterparts. |
| doi_str_mv | 10.1109/ICEE55646.2022.9827189 |
| format | conference_proceeding |
| fullrecord | <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_9827189</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9827189</ieee_id><sourcerecordid>9827189</sourcerecordid><originalsourceid>FETCH-LOGICAL-i1149-7b10f0ec1b5edce6456f7de863c19e283418a38479eede32af83189e791bb3363</originalsourceid><addsrcrecordid>eNotkMtKw0AUQEdBsNR-gSDzA6lz5z3LGqotFC2ouCyTyY2Opkm5rQT9egt2dXaHw2HsBsQUQITbZTmfG2O1nUoh5TR46cCHMzYJzoO1RnvhHZyzkbRaFsFId8km-_2nEEKB9z6YEXtb5PcPvkZqetrGLiGPXc1X_cDX_YDEn3e5O1Df5cTvchcp_2LNH_GbYnvEYejpiy8i1UMk5LOUsEWKh56u2EUT2z1OThyz1_v5S7koVk8Py3K2KjKADoWrQDQCE1QG64RWG9u4Gr1VCQJKrzT4qLx2AbFGJWPjj-kBXYCqUsqqMbv-92ZE3OwobyP9bE4r1B_SBlNw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>High Performance and Low Power Spintronic Binarized Neural Network Hardware Accelerator</title><source>IEEE Xplore All Conference Series</source><creator>Nasab, Milad Tanavardi ; Amirany, Arefe ; Moaiyeri, Mohammad Hossein ; Jafari, Kian</creator><creatorcontrib>Nasab, Milad Tanavardi ; Amirany, Arefe ; Moaiyeri, Mohammad Hossein ; Jafari, Kian</creatorcontrib><description>Neural networks have shown a high ability to model and solve complex problems. Hardware implementation of the neural network can also increase the efficiency of this system and, in particular neural network hardware accelerators. This paper proposes a high-performance and low-power spintronic binarized neural network hardware accelerator using the nonvolatile feature of the magnetic tunnel junction (MTJ) and low leakage current of carbon nanotube field-effect transistors (CNTFET). It is also noteworthy that the proposed design in this paper can implement the hard-limit activation function. Simulation results indicate the neural network implemented using the proposed design in this paper consumes 11% to 98% lower power, occupies 64% to 69% lower area, and offers 29% to 99% lower power delay area product (PDAP) than the state-of-the-art counterparts.</description><identifier>EISSN: 2642-9527</identifier><identifier>EISBN: 9781665480871</identifier><identifier>EISBN: 1665480874</identifier><identifier>DOI: 10.1109/ICEE55646.2022.9827189</identifier><language>eng ; jpn</language><publisher>IEEE</publisher><subject>Binarized neural network hardware accelerator ; CNTFET ; Hardware ; Low power design ; Memory management ; MTJ ; Neural network hardware ; Nonvolatile memory ; Power demand ; Simulation ; System performance ; XNOR-Net</subject><ispartof>2022 30th International Conference on Electrical Engineering (ICEE), 2022, p.774-778</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9827189$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,27902,54530,54907</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9827189$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Nasab, Milad Tanavardi</creatorcontrib><creatorcontrib>Amirany, Arefe</creatorcontrib><creatorcontrib>Moaiyeri, Mohammad Hossein</creatorcontrib><creatorcontrib>Jafari, Kian</creatorcontrib><title>High Performance and Low Power Spintronic Binarized Neural Network Hardware Accelerator</title><title>2022 30th International Conference on Electrical Engineering (ICEE)</title><addtitle>ICEE</addtitle><description>Neural networks have shown a high ability to model and solve complex problems. Hardware implementation of the neural network can also increase the efficiency of this system and, in particular neural network hardware accelerators. This paper proposes a high-performance and low-power spintronic binarized neural network hardware accelerator using the nonvolatile feature of the magnetic tunnel junction (MTJ) and low leakage current of carbon nanotube field-effect transistors (CNTFET). It is also noteworthy that the proposed design in this paper can implement the hard-limit activation function. Simulation results indicate the neural network implemented using the proposed design in this paper consumes 11% to 98% lower power, occupies 64% to 69% lower area, and offers 29% to 99% lower power delay area product (PDAP) than the state-of-the-art counterparts.</description><subject>Binarized neural network hardware accelerator</subject><subject>CNTFET</subject><subject>Hardware</subject><subject>Low power design</subject><subject>Memory management</subject><subject>MTJ</subject><subject>Neural network hardware</subject><subject>Nonvolatile memory</subject><subject>Power demand</subject><subject>Simulation</subject><subject>System performance</subject><subject>XNOR-Net</subject><issn>2642-9527</issn><isbn>9781665480871</isbn><isbn>1665480874</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2022</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkMtKw0AUQEdBsNR-gSDzA6lz5z3LGqotFC2ouCyTyY2Opkm5rQT9egt2dXaHw2HsBsQUQITbZTmfG2O1nUoh5TR46cCHMzYJzoO1RnvhHZyzkbRaFsFId8km-_2nEEKB9z6YEXtb5PcPvkZqetrGLiGPXc1X_cDX_YDEn3e5O1Df5cTvchcp_2LNH_GbYnvEYejpiy8i1UMk5LOUsEWKh56u2EUT2z1OThyz1_v5S7koVk8Py3K2KjKADoWrQDQCE1QG64RWG9u4Gr1VCQJKrzT4qLx2AbFGJWPjj-kBXYCqUsqqMbv-92ZE3OwobyP9bE4r1B_SBlNw</recordid><startdate>20220517</startdate><enddate>20220517</enddate><creator>Nasab, Milad Tanavardi</creator><creator>Amirany, Arefe</creator><creator>Moaiyeri, Mohammad Hossein</creator><creator>Jafari, Kian</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>20220517</creationdate><title>High Performance and Low Power Spintronic Binarized Neural Network Hardware Accelerator</title><author>Nasab, Milad Tanavardi ; Amirany, Arefe ; Moaiyeri, Mohammad Hossein ; Jafari, Kian</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i1149-7b10f0ec1b5edce6456f7de863c19e283418a38479eede32af83189e791bb3363</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng ; jpn</language><creationdate>2022</creationdate><topic>Binarized neural network hardware accelerator</topic><topic>CNTFET</topic><topic>Hardware</topic><topic>Low power design</topic><topic>Memory management</topic><topic>MTJ</topic><topic>Neural network hardware</topic><topic>Nonvolatile memory</topic><topic>Power demand</topic><topic>Simulation</topic><topic>System performance</topic><topic>XNOR-Net</topic><toplevel>online_resources</toplevel><creatorcontrib>Nasab, Milad Tanavardi</creatorcontrib><creatorcontrib>Amirany, Arefe</creatorcontrib><creatorcontrib>Moaiyeri, Mohammad Hossein</creatorcontrib><creatorcontrib>Jafari, Kian</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nasab, Milad Tanavardi</au><au>Amirany, Arefe</au><au>Moaiyeri, Mohammad Hossein</au><au>Jafari, Kian</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>High Performance and Low Power Spintronic Binarized Neural Network Hardware Accelerator</atitle><btitle>2022 30th International Conference on Electrical Engineering (ICEE)</btitle><stitle>ICEE</stitle><date>2022-05-17</date><risdate>2022</risdate><spage>774</spage><epage>778</epage><pages>774-778</pages><eissn>2642-9527</eissn><eisbn>9781665480871</eisbn><eisbn>1665480874</eisbn><abstract>Neural networks have shown a high ability to model and solve complex problems. Hardware implementation of the neural network can also increase the efficiency of this system and, in particular neural network hardware accelerators. This paper proposes a high-performance and low-power spintronic binarized neural network hardware accelerator using the nonvolatile feature of the magnetic tunnel junction (MTJ) and low leakage current of carbon nanotube field-effect transistors (CNTFET). It is also noteworthy that the proposed design in this paper can implement the hard-limit activation function. Simulation results indicate the neural network implemented using the proposed design in this paper consumes 11% to 98% lower power, occupies 64% to 69% lower area, and offers 29% to 99% lower power delay area product (PDAP) than the state-of-the-art counterparts.</abstract><pub>IEEE</pub><doi>10.1109/ICEE55646.2022.9827189</doi><tpages>5</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | EISSN: 2642-9527 |
| ispartof | 2022 30th International Conference on Electrical Engineering (ICEE), 2022, p.774-778 |
| issn | 2642-9527 |
| language | eng ; jpn |
| recordid | cdi_ieee_primary_9827189 |
| source | IEEE Xplore All Conference Series |
| subjects | Binarized neural network hardware accelerator CNTFET Hardware Low power design Memory management MTJ Neural network hardware Nonvolatile memory Power demand Simulation System performance XNOR-Net |
| title | High Performance and Low Power Spintronic Binarized Neural Network Hardware Accelerator |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T04%3A47%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=High%20Performance%20and%20Low%20Power%20Spintronic%20Binarized%20Neural%20Network%20Hardware%20Accelerator&rft.btitle=2022%2030th%20International%20Conference%20on%20Electrical%20Engineering%20(ICEE)&rft.au=Nasab,%20Milad%20Tanavardi&rft.date=2022-05-17&rft.spage=774&rft.epage=778&rft.pages=774-778&rft.eissn=2642-9527&rft_id=info:doi/10.1109/ICEE55646.2022.9827189&rft.eisbn=9781665480871&rft.eisbn_list=1665480874&rft_dat=%3Cieee_CHZPO%3E9827189%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i1149-7b10f0ec1b5edce6456f7de863c19e283418a38479eede32af83189e791bb3363%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=9827189&rfr_iscdi=true |