A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference

This paper presents an SRAM-based analog Compute-in-Memory (CiM) macro in 22 nm CMOS process. By introducing a C-2C capacitor ladder-based charge domain computing scheme, the CiM prototype chip demonstrates 2k multiply-accumulation (MAC) operations in one clock cycle and achieves 32.2 TOPS/W peak en...

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Bibliographic Details
Main Authors: Wang, Hechen, Liu, Renzhi, Dorrance, Richard, Dasalukunte, Deepak, Liu, Xiaosen, Lake, Dan, Carlton, Brent, Wu, May
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
CMOS process
Energy efficiency
Linearity
Prototypes
Random access memory
Very large scale integration
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Summary:This paper presents an SRAM-based analog Compute-in-Memory (CiM) macro in 22 nm CMOS process. By introducing a C-2C capacitor ladder-based charge domain computing scheme, the CiM prototype chip demonstrates 2k multiply-accumulation (MAC) operations in one clock cycle and achieves 32.2 TOPS/W peak energy efficiency and 4.0 TOPS/mm 2 peak area efficiency with 8-bit precision in both input activation and weight. A variety of analog impairment factors were analyzed during the testchip implementation to ensure sufficiently high multibit linearity.
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46769.2022.9830322