Combined unsigned and two's complement hybrid squarers

Designs for high-speed combined squarers, capable of operating on either unsigned or two's complement numbers, are presented. High speed is achieved in part by using a modestly sized ROM table to generate the less significant bits of the square, and combinational logic to generate the more sign...

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Bibliographic Details
Main Authors: Walters, E.G., Schlessman, J., Schulte, M.J.
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Computer science
Delay estimation
Design engineering
Digital arithmetic
Digital signal processing
Laboratories
Logic design
Read only memory
Symmetric matrices
Online Access:Request full text
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Description
Summary:Designs for high-speed combined squarers, capable of operating on either unsigned or two's complement numbers, are presented. High speed is achieved in part by using a modestly sized ROM table to generate the less significant bits of the square, and combinational logic to generate the more significant bits. These squarers have a shorter carry propagate chain in the final adder and a smaller amount of combinational logic than previous hybrid designs. Area and delay estimates indicate that the combined hybrid squarers presented in this paper have between 28% and 64% percent less area and between 9% and 15% percent less delay than previous unsigned hybrid squarers for 32-bit operands.
ISSN:1058-6393
2576-2303
DOI:10.1109/ACSSC.2001.987046