Hybrid BIST using partially rotational scan

Developed a partially rotational scan (PRS) register used for the n-detection BIST (built-in self-test) that can detect not only delay faults but also unmodeled faults. The developed circuit consists of a shift register with partial rotation. Also presents a procedure for selecting test vectors from...

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Bibliographic Details
Main Authors: Ichino, K., Asakawa, T., Fukumoto, S., Iwasaki, K., Kajihara, S.
Format: Conference Proceeding
Language:English
Subjects:
Automatic test pattern generation
Automatic testing
Built-in self-test
Circuit faults
Circuit testing
Computer simulation
Delay
Electrical fault detection
Fault detection
Shift registers
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Description
Summary:Developed a partially rotational scan (PRS) register used for the n-detection BIST (built-in self-test) that can detect not only delay faults but also unmodeled faults. The developed circuit consists of a shift register with partial rotation. Also presents a procedure for selecting test vectors from ATPG (automatic test pattern generation) ones. This testing method enables at-speed testing and the stuck-at fault coverage of n/spl times/100% by using subset of the ATPG vectors. And it drastically reduces the number of vectors input from an external low-speed tester. Computer simulations of stuck-at fault coverage are conducted on ISCAS'85, ISCAS'89, and ITC'99 circuits for detection times n of 1, 2, 3, 5, 10, and 15. They show that the compaction rates of the ATPG test vectors range from 52.4% (s713) to 0.9% (c499) of origin. This result demonstrates that the PRS register can accomplish low-cost, at-speed testing.
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2001.990313