Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters

Modern high-performance computing architectures (Multicore, GPU, Manycore) are based on tightly-coupled clusters of processing elements, physically implemented as rectangular tiles. Their size and aspect ratio strongly impact the achievable operating frequency and energy efficiency, but they should...

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Bibliographic Details
Main Authors: Paulin, Gianna, Cavalcante, Matheus, Scheffler, Paul, Bertaccini, Luca, Zhang, Yichao, Gurkaynak, Frank, Benini, Luca
Format: Conference Proceeding
Language:English
Subjects:
Architecture
Floorplanning
Graphics processing units
High performance computing
Layout
Microprocessors
Multicore processing
Soft Blocks
Very large scale integration
VLSI Architectures
Online Access:Request full text
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Summary:Modern high-performance computing architectures (Multicore, GPU, Manycore) are based on tightly-coupled clusters of processing elements, physically implemented as rectangular tiles. Their size and aspect ratio strongly impact the achievable operating frequency and energy efficiency, but they should be as flexible as possible to achieve a high utilization for the top-level die floorplan. In this paper, we explore the flexibility range for a high-performance cluster of RISC-V cores with shared L1 memory used to build scalable accelerators, with the goal of establishing a hierarchical implementation methodology where clusters can be modeled as soft tiles to achieve optimal die utilization.
ISSN:2159-3477
DOI:10.1109/ISVLSI54635.2022.00021