A Harmonic-Mixing PLL Architecture for Millimeter-Wave Application

• Published in: IEEE journal of solid-state circuits 2022-12, Vol.57 (12), p.3552-3566
• Main Authors: Yang, Dihang, Murphy, David, Darabi, Hooman, Behzad, Arya, Abidi, Asad A., Au, Stephen C., Mundlapudi, Sraavan R., Shi, Kejian, Leng, Weiyu
• Format: Article
• Language: English
• Subjects: Amplification; coupled voltage-controlled oscillator (VCO); Delta-sigma modulation; delta–sigma modulator (DSM); Figure of merit; fractional-N PLL; frequency synthesizer; Frequency synthesizers; harmonic mixing; heterodyne phase-locked loop (PLL); millimeter wave (mm-wave); Millimeter waves; Mixers; Phase locked loops; Phase noise; PLL noise optimization; subsampling; Synthesis; Voltage controlled oscillators
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2022.3209614

A low-noise synthesizer design in the millimeter-wave (mm-wave) range is complicated by the invariably large closed-loop gain and the high operation frequency of the voltage-controlled oscillator (VCO). To overcome these challenges, this work proposes a harmonic-mixing synthesizer system with a 188-dB figure-of-merit mm-wave VCO. The synthesizer extends the bandwidth to 5 MHz, thereby suppressing VCO noise. Importantly, DSM is not amplified by the f_{\mathrm{ VCO}}/f_{\mathrm{ ref}} gain of the system. A prototype employing a 74-MHz reference achieves a −250-dB phase-locked loop (PLL) figure of merit with a measured 88-fs rms jitter.