A 1 MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

A 2nd-order continuous-time quadrature bandpass /spl Sigma//spl Delta/ modulator with 1 MHz IF clocked at 100 MHz digitizes I and Q inputs with SNDR of 56.2 dB for 1 MHz bandwidth inputs. The 0.65 /spl mu/m BiCMOS chip consumes 21.8 mW at 2.7 V, and operates with a clock-frequency range of 25-100 MH...

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Bibliographic Details
Published in:2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) 2002, Vol.1, p.214-461 vol.1
Main Authors: Henkel, F., Langmann, U., Hanke, A., Heinen, S., Wagner, E.
Format: Article
Language:English
Subjects:
Band pass filters
Circuits
Clocks
Computed tomography
Delta-sigma modulation
Feedback
Frequency
Receivers
Transfer functions
Voltage
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Description
Summary:A 2nd-order continuous-time quadrature bandpass /spl Sigma//spl Delta/ modulator with 1 MHz IF clocked at 100 MHz digitizes I and Q inputs with SNDR of 56.2 dB for 1 MHz bandwidth inputs. The 0.65 /spl mu/m BiCMOS chip consumes 21.8 mW at 2.7 V, and operates with a clock-frequency range of 25-100 MHz.
ISSN:0193-6530
DOI:10.1109/ISSCC.2002.993012