Bitwise ELD Compensation in Δ∑ Modulators

Excess loop delay (ELD) in high speed continuoustime (CT) Delta-Sigma-Modulators (DSMs) imposes design challenges and limits the use of high resolution, e.g. successiveapproximation-register (SAR) based internal quantizers, as usual compensation techniques like the use of a direct path around the qu...

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Bibliographic Details
Main Authors: Pietzko, Michael, Ungethum, Jonathan, Kauffman, John G., Li, Qiang, Ortmanns, Maurits
Format: Conference Proceeding
Language:English
Subjects:
ADC
Circuits and systems
Continuous-time (CT)
Delays
Delta-Sigma-Modulator (DSM)
Distributed feedback devices
excess loop delay (ELD)
Feedback loop
Filtering theory
Modulation
SAR
Software packages
wideband
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Summary:Excess loop delay (ELD) in high speed continuoustime (CT) Delta-Sigma-Modulators (DSMs) imposes design challenges and limits the use of high resolution, e.g. successiveapproximation-register (SAR) based internal quantizers, as usual compensation techniques like the use of a direct path around the quantizer come with increased swings and reduced maximum stable amplitude (MSA). In this paper, two bitwise ELD compensation approaches applicable to cascade-of-integrators with distributed feedback (CIFB) loop filters are proposed, which alleviate this problem for SAR and other multi-step quantizers by sequentially feeding bits into the feedback loop when they are available (MSB first, LSB last). Loop-filter equivalence for such bitwise ELD compensation is analytically derived. System-level simulations using Matlab & Simulink for exemplary 4-bit 2nd, 3rd and 4th-order modulators show 40% reduction of the last integrator output swing compared to the conventional direct path compensation. This potentially allows to avoid the swing, quantizer scaling and noise trade-offs due to ELD in state of the art designs.
ISSN:2158-1525
DOI:10.1109/ISCAS48785.2022.9937305