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A Real Time Super Resolution Accelerator with Tilted Layer Fusion
Deep learning based superresolution achieves high-quality results, but its heavy computational workload, large buffer, and high external memory bandwidth inhibit its usage in mobile devices. To solve the above issues, this paper proposes a real-time hardware accelerator with the tilted layer fusion...
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Main Authors: | , , |
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Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Request full text |
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Summary: | Deep learning based superresolution achieves high-quality results, but its heavy computational workload, large buffer, and high external memory bandwidth inhibit its usage in mobile devices. To solve the above issues, this paper proposes a real-time hardware accelerator with the tilted layer fusion method that reduces the external DRAM bandwidth by 92% and just needs 102KB on-chip memory. The design implemented with a 40nm CMOS process achieves 1920xl080@60fps throughput with 544. 3K gate count when running at 600MHz; it has higher throughput and lower area cost than previous designs. |
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ISSN: | 2158-1525 |
DOI: | 10.1109/ISCAS48785.2022.9937448 |