3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS

As the technology scaling has happened, logic performance has improved at a much faster rate than SRAM performance. Therefore, in SRAMs, required performance improvement is achieved by design and architecture level changes. This work presents pipelined hierarchical SRAM and compares it with a conven...

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Bibliographic Details
Main Authors: Srivastav, Mukesh Kumar, Rimjhim, Mishra, Roshan, Grover, Anuj, Dhori, Kedar Janardan, Rawat, Harsh
Format: Conference Proceeding
Language:English
Subjects:
Burst mode
Circuits and systems
CMOS technology
Costs
Hierarchical bitline
Integrated circuit modeling
L2 cache
low energy
low power
Pipeline
Pipeline processing
Random access memory
SRAM
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Summary:As the technology scaling has happened, logic performance has improved at a much faster rate than SRAM performance. Therefore, in SRAMs, required performance improvement is achieved by design and architecture level changes. This work presents pipelined hierarchical SRAM and compares it with a conventional non-hierarchical SRAM design on the axes of Performance, Power, and Area. We show that a pipelined SRAM of size 8192×64 m16 with integrated burst mode, operates at 40% lesser dynamic power and is 31% faster than a conventional non-hierarchical SRAM design in 65nm Low stand-by Power(LSTP) CMOS technology. When compared to hierarchical design, it operates at 19% lesser dynamic power and is 17% faster with an area increase of 5%.
ISSN:2158-1525
DOI:10.1109/ISCAS48785.2022.9937582