Implementation of artificial neural networks on a reconfigurable hardware accelerator

The hardware implementations of three different artificial neural networks are presented. The basis for the implementations is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing f...

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Main Authors: Porrmann, M., Witkowski, U., Kalte, H., Ruckert, U.
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Artificial neural networks
Broadcasting
Field programmable gate arrays
Memory management
Neural network hardware
Postal services
Prototypes
Random access memory
World Wide Web
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creator Porrmann, M.
Witkowski, U.
Kalte, H.
Ruckert, U.
description The hardware implementations of three different artificial neural networks are presented. The basis for the implementations is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing feature maps and basis function networks. Some of the key implementation issues are considered. In particular, the resource efficiency and performance of the presented realizations are discussed.
doi_str_mv 10.1109/EMPDP.2002.994279
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Acceleration
Artificial neural networks
Broadcasting
Field programmable gate arrays
Memory management
Neural network hardware
Postal services
Prototypes
Random access memory
World Wide Web
title Implementation of artificial neural networks on a reconfigurable hardware accelerator
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