Diagnosing Transition Delay Faults under Scan-Based Logic Array

This paper presents a novel diagnostic procedure for transition delay faults (TDFs) using a two-dimensional scan - based test chip architecture. The test chip architecture consists of C-testable blocks (CTBs) and scan registers. Each CTB has the distinguished VH-bijection property that ensures any c...

Full description

Saved in:
Bibliographic Details
Main Authors: Kang, Duo-Yao, Lin, Shiou-Ning, Lee, Kuen-Jong
Format: Conference Proceeding
Language:English
Subjects:
Asia
C-testable blocks
Clocks
Delays
Fault diagnosis
Fault location
Logic arrays
Registers
Test chip
Transition delay fault
VH-bijection
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents a novel diagnostic procedure for transition delay faults (TDFs) using a two-dimensional scan - based test chip architecture. The test chip architecture consists of C-testable blocks (CTBs) and scan registers. Each CTB has the distinguished VH-bijection property that ensures any change on either the vertical or horizontal input of a CTB will lead to changes in both vertical and horizontal outputs. The diagnostic procedure consists of two tests, one for the scan chain test and the other for the whole chip test. Experimental result s show that the required time for a test chip containing 68*68 8-input/8-output CTBs is less than 0.2 seconds when executing the test procedure at 100MHz. The proposed diagnostic procedure can achieve 100% diagnosability for all transition faults in th e test chip.
ISSN:2768-069X
DOI:10.1109/ITCAsia55616.2022.00013