A power minimization technique for arithmetic circuits by cell selection

As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit design. This paper proposes a new design method, in which basic cells are selected from a set of circuits with different...

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Main Authors: Muroyama, T., Ishihara, T., Hyodo, A., Yasuura, T.
Format: Conference Proceeding
Language:English
Subjects:
Arithmetic
Circuits
Minimization
Very large scale integration
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Ishihara, T.
Hyodo, A.
Yasuura, T.
description As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit design. This paper proposes a new design method, in which basic cells are selected from a set of circuits with different structures (symmetrical and asymmetrical) and connections to their terminals are exchanged, according to input-patterns to minimize power consumption. Experimental results for a parallel multiplier demonstrate average 30% power reduction.
doi_str_mv 10.1109/ASPDAC.2002.994933
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subjects Arithmetic
Circuits
Minimization
Very large scale integration
title A power minimization technique for arithmetic circuits by cell selection
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