An Input Buffer with 85dB SFDR for High-Speed Pipeline ADC

This paper presents a high linearity input buffer with proposed two-level bootstrapping scheme for high-speed pipeline ADC. In high input frequency, the parasitic capacitance of active devices and inductance of packaging are the main sources of non-linearity. In order to improve the linearity, the p...

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Bibliographic Details
Main Authors: Huang, Cece, Zhao, Yuanfu, Ji, Yafei, Yang, Xin, Zhang, Tieliang, Gai, Weixin
Format: Conference Proceeding
Language:English
Subjects:
ADC
Bandwidth
CMOS technology
Current measurement
High SFDR
Inductance
Input buffer
Linearity
Packaging
Pipelines
Online Access:Request full text
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Summary:This paper presents a high linearity input buffer with proposed two-level bootstrapping scheme for high-speed pipeline ADC. In high input frequency, the parasitic capacitance of active devices and inductance of packaging are the main sources of non-linearity. In order to improve the linearity, the proposed input buffer drives the bootstrapping block by the output signal instead of the input, which prevents the non-linear sink current from flowing through the inductance, and thus the linearity is improved. The input buffer was designed together with a 14-bit 500MSPS pipeline ADC in a 28nm CMOS technology. The measured results show that the SFDR achieves 85dB at 2 nd Nyquist frequency, which is 8dB larger than the conventional one.
ISSN:2831-3968
DOI:10.1109/ICTA56932.2022.9962993