A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O

This paper presents a 56Gb/s de-serializer with PAM-4 CDR for chiplet optical-I/O in 28nm CMOS. There are two channels in this chip. Each channel consists of a high-performance analog front end (AFE) and a half-rate clock and data recovery (CDR) circuit based on a digital phase interpolator and digi...

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Bibliographic Details
Main Authors: Yang, Yunqi, Zhong, Ming, Ma, Qianli, Lin, Ziyi, Li, Leliang, Li, Guike, Liu, Liyuan, Liu, Jian, Wu, Nanjian, Jia, Haikun, Liu, Xinghui, Qi, Nan
Format: Conference Proceeding
Language:English
Subjects:
clock and data recovery (CDR)
de-serializer
equalization
Integrated optics
Jitter
Optical filters
Optical variables measurement
Optical-I/O
phase interpolation
Phase measurement
Phase noise
Semiconductor device measurement
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Summary:This paper presents a 56Gb/s de-serializer with PAM-4 CDR for chiplet optical-I/O in 28nm CMOS. There are two channels in this chip. Each channel consists of a high-performance analog front end (AFE) and a half-rate clock and data recovery (CDR) circuit based on a digital phase interpolator and digital loop filter. To provide 28-GHz clock signals to both channels, a clock distribution circuit is integrated. Experimental results show that the proposed de-serializer recovers a 56Gb/s PAM-4 input signal with channel loss, achieving an output swing of 1.01-Vppd and 760ps RMS jitter.
ISSN:2831-3968
DOI:10.1109/ICTA56932.2022.9963101