Gate level fault diagnosis in scan-based BIST

A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test vector information and enables location identification of single stuck-at faults to a neighborhood of a few gates through...

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Bibliographic Details
Main Authors: Bayraktaroglu, I., Orailoglu, A.
Format: Conference Proceeding
Language:English
Subjects:
Automatic testing
Built-in self-test
Clocks
Computer science
Design engineering
Dictionaries
Fault diagnosis
Memory
Performance evaluation
Test pattern generators
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Description
Summary:A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test vector information and enables location identification of single stuck-at faults to a neighborhood of a few gates through set operations on small pass/fail dictionaries. The proposed scheme is applicable to multiple stuck-at faults and bridging faults as well. The practical applicability of the suggested ideas is confirmed through numerous experimental runs on all three fault models.
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2002.998301