Statistical timing driven partitioning for VLSI circuits

Presents statistical-timing driven partitioning for performance optimization. We show that by using the concept of node criticality we can enhance the Fiduccia-Mattheyses (FM) partitioning algorithm to achieve, on average, around 20% improvements in terms of timing, among partitions with the same cu...

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Bibliographic Details
Main Authors: Ababei, C., Bazargan, K.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Circuits
Delay estimation
Design optimization
Partitioning algorithms
Process design
Process planning
Timing
Very large scale integration
Wire
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Description
Summary:Presents statistical-timing driven partitioning for performance optimization. We show that by using the concept of node criticality we can enhance the Fiduccia-Mattheyses (FM) partitioning algorithm to achieve, on average, around 20% improvements in terms of timing, among partitions with the same cut size. By incorporating mechanisms for timing optimization at the partitioning level, we facilitate wire-planning at high levels of the design process.
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2002.998465