Animate vision demonstrator utilising reconfigurable system designs

The justifications for migration from discrete logic implementations to field programmable devices (PLD/FPGA) for state machine, logic replacement and datapath operations are well known and established. They offer the user a flexible design methodology at a gate level for a low initial investment an...

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Main Authors: Shelley, A.J, Seed, N.L
Format: Conference Proceeding
Language:English
Subjects:
Computer vision and image processing techniques
Graphics techniques
Logic and switching circuits
Logic circuits
Memory circuits
Optical information, image and video signal processing
Parallel architecture
Semiconductor integrated circuits
Semiconductor storage
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Seed, N.L
description The justifications for migration from discrete logic implementations to field programmable devices (PLD/FPGA) for state machine, logic replacement and datapath operations are well known and established. They offer the user a flexible design methodology at a gate level for a low initial investment and demand no early commitments to high volumes. Furthermore, the capabilities of a volatile static memory based FPGA technology extend well beyond the limited scope of integration enhancement. This paper outlines a reconfigurable image processing architecture (RIPA) and its integration into an animate vision demonstrator.
doi_str_mv 10.1049/cp:19950709
format conference_proceeding
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ispartof Fifth International Conference on Image Processing and its Applications, 1995, p.500-504
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Computer vision and image processing techniques
Graphics techniques
Logic and switching circuits
Logic circuits
Memory circuits
Optical information, image and video signal processing
Parallel architecture
Semiconductor integrated circuits
Semiconductor storage
title Animate vision demonstrator utilising reconfigurable system designs
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