Check node unit for LDPC decoders based on one-hot data representation of messages

A novel check node unit architecture for low-density parity check (LDPC) decoders, which avoids the usage of carry-based comparators for the computation of the required first and second minimum values, is presented. It relies on a one-hot representation of the input messages’ magnitude, obtained by...

Full description

Saved in:
Bibliographic Details
Published in:Electronics letters 2015-06, Vol.51 (12), p.907-908
Main Authors: Boncalo, O, Amaricai, A, Savin, V, Declercq, D, Ghaffari, F
Format: Article
Language:English
Subjects:
carry‐based comparators
check node unit architecture
comparators (circuits)
Computer Science
error correction analysis
error correction codes
Information and communications
Information Theory
LDPC decoder
leading zero counter
message one‐hot data representation
OR tree
parity check codes
q‐to‐2q decoders
trees (mathematics)
Citations: Items that this one cites
Items that cite this one
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A novel check node unit architecture for low-density parity check (LDPC) decoders, which avoids the usage of carry-based comparators for the computation of the required first and second minimum values, is presented. It relies on a one-hot representation of the input messages’ magnitude, obtained by q-to-2q decoders. The two minimums are computed using an OR tree and a modified leading zero counter. The proposed architecture is imprecise, as the second minimum is not computed correctly when it is equal to the first one. The implementation results and the analysis of the error correction capability show that the proposed imprecise unit is highly suited for high rate LDPC codes; it presents up to 30% better hardware cost, a higher working frequency, while the loss of the decoding capability is negligible with respect to standard implementations.
ISSN:0013-5194
1350-911X
1350-911X
DOI:10.1049/el.2015.0108