FPGA-based parallel process for Walsh–Hadamard transform

A field-programmable gate array-based reconfigurable parallel computing unit to calculate the Walsh–Hadamard transform is proposed. The architecture can process long-duration signals with a large number of samples. Obtained results demonstrate its versatility and usefulness in applications requiring...

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Bibliographic Details
Published in:Electronics letters 2020-09, Vol.56 (20), p.1039-1041
Main Authors: Reynoso-Godinez, R, Rodriguez-Donate, C, Lopez-Ramirez, M, Garcia-Guevara, F.M
Format: Article
Language:English
Subjects:
Circuits and systems
Cyclone II 2C20
Cyclone IV EP4CE22
digital signal processing
digital signal processing chips
field programmable gate arrays
field‐programmable gate array
FPGA
Hadamard transforms
mathematics computing
parallel process
parallel processing
reconfigurable architectures
reconfigurable parallel computing unit
Walsh–Hadamard transform
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Summary:A field-programmable gate array-based reconfigurable parallel computing unit to calculate the Walsh–Hadamard transform is proposed. The architecture can process long-duration signals with a large number of samples. Obtained results demonstrate its versatility and usefulness in applications requiring online digital signal processing, utilising few resources in low-cost devises as Cyclone II 2C20 and Cyclone IV EP4CE22.
ISSN:0013-5194
1350-911X
1350-911X
DOI:10.1049/el.2020.1773