Multi-standard high-throughput and low-power quasi-cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards

• Published in: IET circuits, devices & systems devices & systems, 2016-03, Vol.10 (2), p.111-120
• Main Authors: Kanchetla, Vijaya Kumar, Shrestha, Rahul, Paily, Roy
• Format: Article
• Language: English
• Subjects: Accuracy; Algorithms; Architecture; CMOS integrated circuits; CMOS process; Codes; column layered decoding technique; complementary metal oxide semiconductor; Computer architecture; convergence; convergence speed; cyclic codes; Decoders; Decoding; Density; Error correcting codes; frequency 149 MHz; Graph representations; Handles; IEEE 802.11n; IEEE 802.16e; Interoperability; Low density parity check codes; matrix algebra; matrix permutation method; multiple code-rate; multistandard high throughput QC-LDPC decoder; Parallel processing; Parity; parity check codes; parity check matrix; Permutations; power 146 mW; quasicyclic low density parity check decoder; register file; size 90 nm; voltage 0.9 V; WiMax; Wireless communication; Wireless communications; wireless fidelity communication standard; wireless LAN; worldwide interoperability for microwave access
• ISSN: 1751-858X; 1751-8598; 1751-8598
• DOI: 10.1049/iet-cds.2014.0347

This study presents a reconfigurable quasi-cyclic low density parity check (QC-LDPC) decoder for IEEE 802.16e worldwide interoperability for microwave access and IEEE 802.11n wireless fidelity communication standards. It supports multiple code-rates of 1/2, 2/3, 3/4, 5/6 and its architecture has been designed based on column layered decoding technique to enhance the convergence speed. The authors have suggested a register file based approach to handle the shift property of the modified parity check matrix and a modified version of the matrix permutation method has been introduced to reduce the number of check nodes which handle multiple messages. In addition, parallel processing has been incorporated in the decoder architecture to attain higher achievable throughput. This QC-LDPC decoder is implemented in 90 nm CMOS process and is post-layout simulated. It can achieve a throughput of 796 Mbps for a code-rate of 5/6. With 0.9 V supply, it consumes 146 mW of total power at 149 MHz clock frequency.