Design and implementation of image kernels using reversible logic gates

• Published in: IET image processing 2020-12, Vol.14 (16), p.4110-4121
• Main Authors: Raveendran, Sithara, Edavoor, Pranose Jose, Yernad Balachandra, Nithin Kumar, Moodabettu Harishchandra, Vasantha
• Format: Article
• Language: English
• Subjects: 512$512×512 standard images; ancilla inputs; edge detection; field programmable gate arrays; filter kernel; filtered images; filtering enhancing; gate count; image enhancement; image kernels; logic design; logic gates; Research Article; reversible logic based design; reversible logic gates; reversible logic literature
• ISSN: 1751-9659; 1751-9667
• DOI: 10.1049/iet-ipr.2019.1681

This study presents the implementation of image kernels used for filtering and enhancing the images using reversible logic gates, a first in reversible logic literature. Image enhancement/filtering is achieved by performing convolution of an image with a filter kernel. This work proposes reversible logic based design and implementation of six filter kernels. The filter kernels implemented are Gaussian blur, Laplacian outline, Sobel, Emboss, Sharpen and Prewitt edge detection. The kernels are implemented individually using reversible logic gates and the designs are measured in terms of quantum cost, garbage outputs, ancilla inputs and gate count. The functional verification is carried out using $512 \times 512$512×512 standard images on Kintex 7 FPGA platform. The filtered images from the proposed design have an average structural similarity index of 0.92.