GEOMETRICAL SCALING EFFECTS IN HIGH PERMITTIVITY CAPACITORS

In integrated circuit designs, smaller is better; high permittivity films allow circuit designers to save substrate space, but the small geometries of such devices introduce parasitic effects. In this work we investigate the relationship between device geometry and capacitance density, quality facto...

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Bibliographic Details
Published in:Integrated ferroelectrics 2006-11, Vol.80 (1), p.437-442
Main Authors: PERVEZ, NADIA K., PARK, JAEHOON, LU, JIWEI, STEMMER, SUSANNE, YORK, ROBERT A.
Format: Article
Language:English
Subjects:
barium strontium titanate
bismuth zinc niobate
dielectric properties
Inegrated passives
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Summary:In integrated circuit designs, smaller is better; high permittivity films allow circuit designers to save substrate space, but the small geometries of such devices introduce parasitic effects. In this work we investigate the relationship between device geometry and capacitance density, quality factor, and leakage current density. The devices in this study have electrode areas ranging from 12 × 12 μm 2 to 45 × 45 μm 2 . For each electrode area we have structures with 5 μm, 7.5 μm, 10 μm, 12.5 μm and 15 μm mesa ledges.
ISSN:1058-4587
1607-8489
DOI:10.1080/10584580600663235