Current mirror featuring DTMOS for analog single-event transient mitigation in space application

• Published in: Semiconductor science and technology 2020-08, Vol.35 (8), p.85028
• Main Authors: Liu, Jingtian, Xu, Xinyu, Sun, Qian, Liang, Bin, Chen, Jianjun, Chi, Yaqing, Guo, Yang
• Format: Article
• Language: English
• Subjects: analog single-event transient; current mirrors; dynamic threshold-voltage MOSFETs; radiation-hardened-by-design
• ISSN: 0268-1242; 1361-6641
• DOI: 10.1088/1361-6641/ab9a17

Dynamic threshold-voltage MOSFETs (DTMOSs) with bulk and gate tied together are commonly used in ultra-low voltage applications. Since the threshold voltage of the device is a function of its gate voltage, and the current-driving capability is boosted as the gate-source voltage increases, it has the potential to be applied in the community of radiation-hardened IC circuits. This paper firstly demonstrates that DTMOS is particularly suitable for analog single-event transient (ASET) mitigation in cascode current mirrors with negligible penalty. A basic current mirror and a cascode current mirror are modelled to analyze the devices in DTMOS configuration, and compare radiation performance with standard MOSFETs. Simulation results demonstrate that the DTMOS scheme reduces charge collection, and suppresses single-event effect-induced perturbation effectively in the cascode current mirror, while playing a detrimental role in basic current mirrors due to the well-known bipolar effect. This technique provides a novel method for mitigating ASET disturbances for the designers of spaceborne ICs.