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Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET
This paper reports the DC, RF and circuit-level performance analysis of short-channel Ge/Si based source-pocket engineered (SPE) vertical heterojunction tunnel field effect transistors (Ge/Si SPE-V-HTFETs) with and without a heterogeneous gate dielectric (HGD) structure for the first time. The DC pe...
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Published in: | Semiconductor science and technology 2020-10, Vol.35 (10), p.105014 |
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Main Authors: | , , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | This paper reports the DC, RF and circuit-level performance analysis of short-channel Ge/Si based source-pocket engineered (SPE) vertical heterojunction tunnel field effect transistors (Ge/Si SPE-V-HTFETs) with and without a heterogeneous gate dielectric (HGD) structure for the first time. The DC performance parameters in terms of ION/IOFF and subthreshold swing (SS) are investigated for the proposed V-HTFETs. The average SS for the proposed V-HTFET with an HGD is found to be as low as 20 mV dec−1 compared to V-HTFET without any HGD (26 mV dec−1) at VDS = 0.5 V. The proposed Ge/Si SPE-V-HTFET with an HGD possesses higher cut-off frequency of 502 GHz and maximum frequency of oscillation of 2.33 THz at VDS = 0.5 V over the Ge/Si SPE-V-HTFET without any HGD which possesses cut-off frequency of 273 GHz and maximum frequency of oscillation of 1.47 THz. The proposed Ge/Si SPE-V-HTFET with and without an HGD have then been used for designing a basic current mirror circuit. Device-level study has been carried out using SILVACO ATLASTM TCAD simulator while the circuit-level investigation has been performed using the look up table based Verilog-A models in the CADENCE Virtuoso tool. The performances of the Ge/Si SPE-V-HTFET with HGD based current mirror circuit is observed to be better than the corresponding current mirror circuit designed by Ge/Si SPE-V-HTFET without any HGD. |
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ISSN: | 0268-1242 1361-6641 |
DOI: | 10.1088/1361-6641/aba418 |