Parallel and hierarchical architectures of 4-channel MFP digitizer

• Published in: Journal of physics. Conference series 2018-08, Vol.1065 (5), p.52003
• Main Authors: Angrisani, A., D'Arco, M., Monsurrò, P., Trifiletti, A.
• Format: Article
• Language: English
• Subjects: Analog to digital conversion; Analog to digital converters; Bandwidths; Digital signal processing; Digitization; Physics; Sampling
• ISSN: 1742-6588; 1742-6596
• DOI: 10.1088/1742-6596/1065/5/052003

Two alternative architectures of 4-channel mixing-filtering-processing (MFP) digitizers are presented. Both architectures use four analogue-to-digital converters (ADCs), but differ in terms of layout, and are named parallel and hierarchical. Unlike conventional time-interleaved digitizers, which require ADCs characterized by relaxed sampling rate but critical bandwidth specifications, the proposed architectures are less demanding in terms of both ADCs' sampling rate and bandwidth, thus allowing less noise into the digitizer. Two digital signal processing techniques, needed to combine the digitized streams produced by the ADCs and obtain a digital representation of the input signal, are described for both parallel and hierarchical architectures. These techniques are developed on the basis of suitable error models, also discussed in the paper, and allow removing gain and aliasing errors due to analogue impairments by means of streamline calibration. The results of behavioural simulations carried out to assess the performance of the two alternative 4-channel MFP architectures are finally shown.