Comparative study of C–V-based extraction methods of interface state density for a low-temperature polysilicon thin film

• Published in: Materials research express 2021-08, Vol.8 (8), p.85902
• Main Authors: Lee, Woohui, Oh, Joohee, Chu, Jae Hwan, Choi, Sanggun, Kang, Taewook, Chu, Hyeyong, Kim, Hyoungsub
• Format: Article
• Language: English
• Subjects: Capacitance; capacitance-voltage; Comparative studies; Density; Energy gap; Grain boundaries; interface state density; Low frequencies; Low temperature; low-temperature polysilicon; Polysilicon; Room temperature; Thin films
• ISSN: 2053-1591; 2053-1591
• DOI: 10.1088/2053-1591/ac1aa6

To extract comprehensive and accurate interface state density ( D it ) distribution for a low-temperature polysilicon (LTPS) thin film, three well-established methods based on capacitance–voltage ( C – V ) measurements were compared: high–low frequency capacitance, conductance, and quasi-static (QS) capacitance methods. Because of the strong frequency-dependent response of grain boundary traps within the LTPS, C – V measurements are necessary on p- as well as n-type LTPS films, as they provide D it distribution across the entire LTPS band gap. The QS capacitance method, which uses an optimal high-frequency C – V curve with a minimal grain boundary trap response, provided the best and most comprehensive estimate of D it distribution across the LTPS band gap, even at room temperature (25 °C). Although the narrow extraction ranges of D it were extended toward the mid-gap region by increasing the measurement temperature in both high–low frequency capacitance and conductance methods, the responses of the grain boundary traps still overestimated the D it values near the band edges.