(Invited) Comparative Simulation Study of InAs/Si and All-III-V Hetero Tunnel FETs

Two different nanowire tunnel FETs, based either on the InAs/Si or the In0.53Ga0.47As/InP hetero-system, are investigated by device simulation. Variations of radius, equivalent oxide thickness, local doping, valence band offset, temperature, and the effect of trap-assisted tunneling on the sub-thres...

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Bibliographic Details
Published in:ECS transactions 2015-03, Vol.66 (5), p.157-169
Main Authors: Schenk, Andreas, Sant, Saurabh, Moselund, Kirsten, Riel, Heike
Format: Article
Language:English
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Summary:Two different nanowire tunnel FETs, based either on the InAs/Si or the In0.53Ga0.47As/InP hetero-system, are investigated by device simulation. Variations of radius, equivalent oxide thickness, local doping, valence band offset, temperature, and the effect of trap-assisted tunneling on the sub-threshold slope and the on-current of the transistors are demonstrated.
ISSN:1938-5862
1938-6737
DOI:10.1149/06605.0157ecst