Research on single event effects and hardening design of LDMOS transistors

In this paper, an N-type Lateral Diffused Metal Oxide Semiconductor (LDMOS) device was designed using a heavily doped P+ well and drain N-type buffer layer structure in the BCD process. The hardened mechanism of heavily doped P+ well and drain N-type buffer layer structures was simulated and analyze...

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Bibliographic Details
Published in:Japanese Journal of Applied Physics 2024-08, Vol.63 (8), p.081001
Main Authors: Wang, Ying, Zhou, Wei, Peng, Ling, Chu, Fei, Wang, Zongmin, Kong, Ying, Hu, Guicai, Hu, Yifan
Format: Article
Language:English
Subjects:
Buffer layers
Diffusion layers
Hardening
LDMOS
Metal oxide semiconductors
N-type semiconductors
radiation-harden
Single Event Effects
single-event-burnout (SEB)
single-event-gate-rupture (SEGR)
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Summary:In this paper, an N-type Lateral Diffused Metal Oxide Semiconductor (LDMOS) device was designed using a heavily doped P+ well and drain N-type buffer layer structure in the BCD process. The hardened mechanism of heavily doped P+ well and drain N-type buffer layer structures was simulated and analyzed using a TCAD device simulator. To verify the anti-SEE performance of the LDMOS, the irradiation test was conducted using Ta ion (LET = 79.2 MeV·cm−2 mg−1). The results show that increasing P+ well doping concentration and using buffer layer structure can increase the single event burnout (SEB) voltage of high-voltage LDMOS devices. SEB did not occur within the full operation voltage range.
ISSN:0021-4922
1347-4065
DOI:10.35848/1347-4065/ad6b6b