Graph theory for FPGA minimum configurations

A traditional bottom-up modeling method for minimum configuration numbers is adopted for the study of FPGA minimum configurations. This method is limited ifa large number of LUTs and multiplexers are presented. Since graph theory has been extensively applied to circuit analysis and test, this paper...

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Bibliographic Details
Published in:Journal of semiconductors 2011-11, Vol.32 (11), p.167-171
Main Author: 阮爱武 李文昌 项传银 宋江民 康实 廖永波
Format: Article
Language:English
Subjects:
Blocking
Circuits
CLB
Field programmable gate arrays
FPGA
Graph theory
Graphs
IFA
LUT
Mathematical models
Multiplexers
Semiconductors
图论
复用器
建模方法
配置
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Summary:A traditional bottom-up modeling method for minimum configuration numbers is adopted for the study of FPGA minimum configurations. This method is limited ifa large number of LUTs and multiplexers are presented. Since graph theory has been extensively applied to circuit analysis and test, this paper focuses on the modeling FPGA configurations. In our study, an internal logic block and interconnections of an FPGA are considered as a vertex and an edge connecting two vertices in the graph, respectively. A top-down modeling method is proposed in the paper to achieve minimum configuration numbers for CLB and IOB. Based on the proposed modeling approach and exhaustive analysis, the minimum configuration numbers for CLB and IOB are five and three, respectively.
ISSN:1674-4926
DOI:10.1088/1674-4926/32/11/115018