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Performance evaluation of a PET demonstrator for PET-MR imaging based on monolithic LYSO:Ce scintillators

We are developing a positron emission tomography (PET) insert based on avalanche photodiode (APD) arrays and monolithic LYSO:Ce scintillators for human brain functional studies to be used inside a clinical magnetic resonance imaging (MRI) equipment. In a previous work [1], we demonstrated the perfor...

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Bibliographic Details
Published in:Journal of instrumentation 2011-12, Vol.6 (12), p.C12041-C12041
Main Authors: Sarasola, I, Cuerdo, R, Navarrete, J, Acilu, P García de, Mendes, P Rato, Cela, J M, Oller, J C, Romero, L, Willmott, C
Format: Article
Language:English
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Summary:We are developing a positron emission tomography (PET) insert based on avalanche photodiode (APD) arrays and monolithic LYSO:Ce scintillators for human brain functional studies to be used inside a clinical magnetic resonance imaging (MRI) equipment. In a previous work [1], we demonstrated the performance of our detectors by implementing an experimental setup consisting of two monolithic blocks working in coincidence, which were read out by the first version of an application-specific integrated circuit (ASIC), VATA240, followed by external coincidence and digitalization modules. This preliminary demonstrator showed good spatial resolution at detector level on the order of 2.2 mm full-width at half-maximum (FWHM) and good imaging qualities, which achieved reconstructed images of super(22)Na point sources with spatial resolutions of 2.1 mm FWHM. Nevertheless, we detected image distortions and compressions due to the non-linearities close to the edge of the crystals and the simplicity of that demonstrator with the absence of neighbor blocks [1]. In this work we have implemented a larger scale PET demonstrator, which is based on the new updated ASIC (VATA241) [2] and is formed by two sectors of four monolithic detector blocks placed face-to-face. This new prototype demonstrator has been built for validating the data readout architecture, the coincidence processing implemented in a Xilinx Virtex 5 field programmable gate array (FPGA), as well as the continuous neural networks (NN) training method required to determine the points of entrance over the surface of our monolithic detector blocks.
ISSN:1748-0221
1748-0221
DOI:10.1088/1748-0221/6/12/C12041