Effects of the polarity of highelectric field stressing on power VDMOSFETs parameters

Purpose The purpose of this paper is to study the effects of positive and negative bias stressing on switching performance of power VDMOSFETs used in communication systems. Designmethodologyapproach A positive and a negative highfield stress are applied on the gate oxide of MOS devices and electrica...

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Bibliographic Details
Published in:Microelectronics international 2010-01, Vol.27 (1), p.17-20
Main Authors: El Bitar, R., Salloum, G., Nsouli, B.
Format: Article
Language:English
Subjects:
Electric field effects
Electronic switching systems
Semiconductor devices
Transistors
Voltage
Online Access:Get full text
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Summary:Purpose The purpose of this paper is to study the effects of positive and negative bias stressing on switching performance of power VDMOSFETs used in communication systems. Designmethodologyapproach A positive and a negative highfield stress are applied on the gate oxide of MOS devices and electrical characterization is performed after each period of stress, a comparison is presented. Findings Compared results between the two types of stress show that certain doses of stress can increase the device speed. The underlying changes of the threshold voltage under these two types of stress are referred to as the variation of the gate oxidetrapped charge and interface trap densities. Originalityvalue This paper presents new and original experiments run over a number of metaloxide semiconductor field effect transistor devices to compare the effects of the direction of the applied field on the degradation and the reliability of these structures.
ISSN:1356-5362
DOI:10.1108/13565361011009478