System Level Architecture Evaluation and Optimization : an Industrial Case Study with AMBA3 AXI

This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique deve...

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Bibliographic Details
Published in:Journal of semiconductor technology and science 2005, Vol.5 (4), p.229-236
Main Authors: Lee, Jong-Eun, Kwon, Woo-Cheol, Kim, Tae-Hun, Chung, Eui-Young, Choi, Kyu-Myung, Kong, Jeong-Taek, Eo, Soo-Kwan, Gwilt, David
Format: Article
Language:Korean
Online Access:Get full text
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Summary:This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time.
ISSN:1598-1657
2233-4866