Loading…

Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor

The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display. At the end the p-channel LTPS TFT fabrication, a charge-injection stress with a strong negative drain bias and a positive gate bias are a...

Full description

Saved in:
Bibliographic Details
Published in:Journal of Information Display 2018, Vol.19 (1), p.45-51
Main Authors: Choi, KwangHyun, Sohn, YoungHa, Moon, GeumJu, Kim, YongSang, Jeon, Jae-Hong, Park, KeeChan
Format: Article
Language:Korean
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 51
container_issue 1
container_start_page 45
container_title Journal of Information Display
container_volume 19
creator Choi, KwangHyun
Sohn, YoungHa
Moon, GeumJu
Kim, YongSang
Jeon, Jae-Hong
Park, KeeChan
description The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display. At the end the p-channel LTPS TFT fabrication, a charge-injection stress with a strong negative drain bias and a positive gate bias are applied to reduce the off-current by injecting electrons into the gate insulator near the drain. In this study, the charge density and the length of the charge-injection region in the gate insulator were estimated by comparing the measured TFT characteristics with the simulation models with various charge-injection lengths and charge densities. It was found that the effective length of the charge-injection region was $0.96{\mu}m$ and the charge density was $-3{\times}10^{12}/cm^2$ for the $2-{\mu}m$-channel-length device when $V_{GS}$ was +20 V and $V_{DS}$ was -10 V under the charge-injection stress condition. It was also found, based on the analysis of the electric field distribution under the bias stress condition, that the charge density and the length of the charge-injection region were invariant against the channel length variation. Therefore, the measured TFT characteristics also accorded closely with the simulation models for different channel lengths, such as 4 and $10{\mu}m$, when the same characteristic values of the charge-injection region were employed.
format article
fullrecord <record><control><sourceid>kisti</sourceid><recordid>TN_cdi_kisti_ndsl_JAKO201823952431229</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JAKO201823952431229</sourcerecordid><originalsourceid>FETCH-kisti_ndsl_JAKO2018239524312293</originalsourceid><addsrcrecordid>eNqNjM1KAzEURoNUcKh9h2xcBiZJ528pokhL6cZ9iZk7M7e9TUoSkenTNwUfwNVZfOd8D6xQsmqFrMt6wQpZda0otayf2CpG_C4rrZu6WTcFm3e-ByJ0IydvDeEVem4nE0YQ6I5gE3rHA4x3-IGnCfhFZME5oJz8igTnCwSTfkJePM02zDGZ-yXwiIQ2h2lCJwakM0_BuIgx-fDMHgdDEVZ_XLKXj_evt09xyjMeXB_psHnd7lUpW6W7Sq21VKrT__VujVhQAw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor</title><source>Access via Taylor &amp; Francis (Open Access Collection)</source><creator>Choi, KwangHyun ; Sohn, YoungHa ; Moon, GeumJu ; Kim, YongSang ; Jeon, Jae-Hong ; Park, KeeChan</creator><creatorcontrib>Choi, KwangHyun ; Sohn, YoungHa ; Moon, GeumJu ; Kim, YongSang ; Jeon, Jae-Hong ; Park, KeeChan</creatorcontrib><description>The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display. At the end the p-channel LTPS TFT fabrication, a charge-injection stress with a strong negative drain bias and a positive gate bias are applied to reduce the off-current by injecting electrons into the gate insulator near the drain. In this study, the charge density and the length of the charge-injection region in the gate insulator were estimated by comparing the measured TFT characteristics with the simulation models with various charge-injection lengths and charge densities. It was found that the effective length of the charge-injection region was $0.96{\mu}m$ and the charge density was $-3{\times}10^{12}/cm^2$ for the $2-{\mu}m$-channel-length device when $V_{GS}$ was +20 V and $V_{DS}$ was -10 V under the charge-injection stress condition. It was also found, based on the analysis of the electric field distribution under the bias stress condition, that the charge density and the length of the charge-injection region were invariant against the channel length variation. Therefore, the measured TFT characteristics also accorded closely with the simulation models for different channel lengths, such as 4 and $10{\mu}m$, when the same characteristic values of the charge-injection region were employed.</description><identifier>ISSN: 1598-0316</identifier><identifier>EISSN: 2158-1606</identifier><language>kor</language><ispartof>Journal of Information Display, 2018, Vol.19 (1), p.45-51</ispartof><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>230,314,780,784,885,4024</link.rule.ids></links><search><creatorcontrib>Choi, KwangHyun</creatorcontrib><creatorcontrib>Sohn, YoungHa</creatorcontrib><creatorcontrib>Moon, GeumJu</creatorcontrib><creatorcontrib>Kim, YongSang</creatorcontrib><creatorcontrib>Jeon, Jae-Hong</creatorcontrib><creatorcontrib>Park, KeeChan</creatorcontrib><title>Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor</title><title>Journal of Information Display</title><addtitle>Journal of information display</addtitle><description>The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display. At the end the p-channel LTPS TFT fabrication, a charge-injection stress with a strong negative drain bias and a positive gate bias are applied to reduce the off-current by injecting electrons into the gate insulator near the drain. In this study, the charge density and the length of the charge-injection region in the gate insulator were estimated by comparing the measured TFT characteristics with the simulation models with various charge-injection lengths and charge densities. It was found that the effective length of the charge-injection region was $0.96{\mu}m$ and the charge density was $-3{\times}10^{12}/cm^2$ for the $2-{\mu}m$-channel-length device when $V_{GS}$ was +20 V and $V_{DS}$ was -10 V under the charge-injection stress condition. It was also found, based on the analysis of the electric field distribution under the bias stress condition, that the charge density and the length of the charge-injection region were invariant against the channel length variation. Therefore, the measured TFT characteristics also accorded closely with the simulation models for different channel lengths, such as 4 and $10{\mu}m$, when the same characteristic values of the charge-injection region were employed.</description><issn>1598-0316</issn><issn>2158-1606</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><recordid>eNqNjM1KAzEURoNUcKh9h2xcBiZJ528pokhL6cZ9iZk7M7e9TUoSkenTNwUfwNVZfOd8D6xQsmqFrMt6wQpZda0otayf2CpG_C4rrZu6WTcFm3e-ByJ0IydvDeEVem4nE0YQ6I5gE3rHA4x3-IGnCfhFZME5oJz8igTnCwSTfkJePM02zDGZ-yXwiIQ2h2lCJwakM0_BuIgx-fDMHgdDEVZ_XLKXj_evt09xyjMeXB_psHnd7lUpW6W7Sq21VKrT__VujVhQAw</recordid><startdate>2018</startdate><enddate>2018</enddate><creator>Choi, KwangHyun</creator><creator>Sohn, YoungHa</creator><creator>Moon, GeumJu</creator><creator>Kim, YongSang</creator><creator>Jeon, Jae-Hong</creator><creator>Park, KeeChan</creator><scope>JDI</scope></search><sort><creationdate>2018</creationdate><title>Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor</title><author>Choi, KwangHyun ; Sohn, YoungHa ; Moon, GeumJu ; Kim, YongSang ; Jeon, Jae-Hong ; Park, KeeChan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-kisti_ndsl_JAKO2018239524312293</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>kor</language><creationdate>2018</creationdate><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Choi, KwangHyun</creatorcontrib><creatorcontrib>Sohn, YoungHa</creatorcontrib><creatorcontrib>Moon, GeumJu</creatorcontrib><creatorcontrib>Kim, YongSang</creatorcontrib><creatorcontrib>Jeon, Jae-Hong</creatorcontrib><creatorcontrib>Park, KeeChan</creatorcontrib><collection>KoreaScience</collection><jtitle>Journal of Information Display</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Choi, KwangHyun</au><au>Sohn, YoungHa</au><au>Moon, GeumJu</au><au>Kim, YongSang</au><au>Jeon, Jae-Hong</au><au>Park, KeeChan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor</atitle><jtitle>Journal of Information Display</jtitle><addtitle>Journal of information display</addtitle><date>2018</date><risdate>2018</risdate><volume>19</volume><issue>1</issue><spage>45</spage><epage>51</epage><pages>45-51</pages><issn>1598-0316</issn><eissn>2158-1606</eissn><abstract>The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display. At the end the p-channel LTPS TFT fabrication, a charge-injection stress with a strong negative drain bias and a positive gate bias are applied to reduce the off-current by injecting electrons into the gate insulator near the drain. In this study, the charge density and the length of the charge-injection region in the gate insulator were estimated by comparing the measured TFT characteristics with the simulation models with various charge-injection lengths and charge densities. It was found that the effective length of the charge-injection region was $0.96{\mu}m$ and the charge density was $-3{\times}10^{12}/cm^2$ for the $2-{\mu}m$-channel-length device when $V_{GS}$ was +20 V and $V_{DS}$ was -10 V under the charge-injection stress condition. It was also found, based on the analysis of the electric field distribution under the bias stress condition, that the charge density and the length of the charge-injection region were invariant against the channel length variation. Therefore, the measured TFT characteristics also accorded closely with the simulation models for different channel lengths, such as 4 and $10{\mu}m$, when the same characteristic values of the charge-injection region were employed.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext
identifier ISSN: 1598-0316
ispartof Journal of Information Display, 2018, Vol.19 (1), p.45-51
issn 1598-0316
2158-1606
language kor
recordid cdi_kisti_ndsl_JAKO201823952431229
source Access via Taylor & Francis (Open Access Collection)
title Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T23%3A07%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-kisti&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Modelling%20localized%20charge-injection%20region%20of%20the%20p-channel%20low-temperature%20polycrystalline%20silicon%20thin-film%20transistor&rft.jtitle=Journal%20of%20Information%20Display&rft.au=Choi,%20KwangHyun&rft.date=2018&rft.volume=19&rft.issue=1&rft.spage=45&rft.epage=51&rft.pages=45-51&rft.issn=1598-0316&rft.eissn=2158-1606&rft_id=info:doi/&rft_dat=%3Ckisti%3EJAKO201823952431229%3C/kisti%3E%3Cgrp_id%3Ecdi_FETCH-kisti_ndsl_JAKO2018239524312293%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true