A VLSI Design of a Pipeline Reed-Solomon Decoder

A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error-locator polynomial. The computation of inverse field elements is completely avoided...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on computers 1985-05, Vol.C-34 (5), p.393-403
Main Authors: Shao, H. M., Truong, T. K., Deutsch, L. J., Yuen, J. H., Reed, I. S.
Format: Article
Language:English
Subjects:
Algorithms
Applied sciences
Coding, codes
Computer Operations And Hardware
Computer Simulation
Computer Systems
Exact sciences and technology
Information, signal and communications theory
Mathematics
Pipeline
Reed-Solomon decoder
Signal and communications theory
Space life sciences
systolic array
Telecommunications and information theory
VLSI
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error-locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation. An example illustrating both the pipeline and systolic array aspects of this decoder structure is given for a (15,9) RS code.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.1985.1676579