A 97.7-dB DR 12.3-μW 1-kHz Bandwidth 2nd Order Delta-sigma Modulator with a Fully Differential Class-AB Op-Amp using Floating Class-AB Control

• Published in: Journal of semiconductor technology and science 2023, 23(5), 113, pp.265-272
• Main Authors: Yu, Byeong-Ho, Boo, Jun-Ho, Lim, Jae-Geun, Kim, Hyoung-Jung, Lee, Jae-Hyuk, Ahn, Gil-Cho
• Format: Article
• Language: English
• Subjects: 전기공학
• ISSN: 1598-1657; 2233-4866; 2233-4866; 1598-1657
• DOI: 10.5573/JSTS.2023.23.5.265

This paper presents a 2nd order modified feed-forward (FF) delta-sigma modulator. To reduce power consumption, the proposed analog-to-digital converter (ADC) adopts a class-AB op-amp for the first integrator since it shows an enhanced slew rate with low quiescent current. In addition, a 4-bit asynchronous successive approximation register (SAR) ADC which exhibits low power consumption is employed as a quantizer. A delay is incorporated into the feedback path for stable operation of the feedback loop. The prototype ADC is fabricated in a 28 nm CMOS process, and the core area is 0.095 mm2. It consumes 12.3 μW from 0.8 V (Analog)/0.85 V (Digital) supply voltages at an operating clock frequency of 512 kHz with an oversampling ratio (OSR) of 256. It achieves a dynamic range (DR) of 97.7 dB and a peak signal-to-noise and distortion ratio (SNDR) of 94.8 dB, corresponding to a Schreier figure-of-merit (FoM) of 176.8 dB. KCI Citation Count: 0