A low-power cache with successive tag comparison algorithm

In recent years, power consumption has become one of the most critical design concerns in designing VLSI systems. The reduction of power consumption is inevitably required by the emergence of highly efficient and fast systems, which include CPU (central processor unit), MCU (micro controller unit),...

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Bibliographic Details
Published in:Current applied physics 2005, 5(3), , pp.227-230
Main Authors: Kim, Tae-Chan, Kim, Chulwoo, Chung, Bong-Young, Kim, Soo-Won
Format: Article
Language:English
Subjects:
Cache
Low power consumption
Successive tag algorithm
물리학
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Summary:In recent years, power consumption has become one of the most critical design concerns in designing VLSI systems. The reduction of power consumption is inevitably required by the emergence of highly efficient and fast systems, which include CPU (central processor unit), MCU (micro controller unit), cache, et cetera. This paper introduces a new low-power cache controller with successive tag comparison algorithm. Using these methods, the power consumption of a cache can be reduced. Simulation results show that the power consumption of a cache using the proposed method is reduced by 42% compared with conventional methods.
ISSN:1567-1739
1878-1675
DOI:10.1016/j.cap.2003.09.019